View V6123_1333789.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

R
EM MICROELECTRONIC - MARIN SA
V6123
Digitally Programmable 2,4 and 8 multiplex LCD Driver
Description The V6123 is low multiplex LCD driver. The 2, 4 and 8 way multiplex is digitally programmable by the command byte. The display refresh is handled on chip by an internal RC oscillator via 1 selectable 8 x 60 RAM which holds the LCD content driven by the driver. LCD pixels (or segments) are addressed on a one to one basis with the 8 x 60 bit RAM (a set bit corresponds to an activated LCD pixel). The V6123 has very low dynamic current consumption, typically 175 A at VDD = 5V, VLCD = 7V making it particularly attractive for portable and battery powered products. The wide operating range on supply voltages and temperature offers much application flexibility. The LCD bias generation and frame frequency are generated on chip. The clock signal can be used to shift and to latch the datas into the RAM. Applications Automotive displays Telephones Pagers Portable, battery operated products Large displays (public information panels etc.) Balances and scales Utility meters Typical Operating Conditions Pad Assignment Features Very simple 1-bit interface (see Fig.1) V6123 mux mode 2 with 2 rows and 58 columns V6123 mux mode 4 with 4 rows and 56 columns V6123 mux mode 8 with 8 rows and 52 columns Very simple1-bit interface, reduced to its simplest form Frame frequency on chip by internal RC oscillator Voltage bias and mux signal generation on chip 1 display RAM addressable as 8 X 60 bit words Column driver only mode to have 60 column outputs No busy states No external components needed Blank function for LCD blanking Bit mapped Wide VDD voltage supply range, 2 to 6V Wide VLCD voltage supply range, 2 to 8.5V -40C to +85C temperature range
Fig. 1
Fig. 2
Copyright (c) 2004, EM Microelectronic-Marin SA
1
www.emmicroelectronic.com
R
V6123
Absolute Maximum Ratings
Parameter Supply voltage range LCD supply voltage range Voltage at DI, DO, CLK, FR Voltage at V1 to V3, S1 to S60 Storage temperature range PElectrostatic discharge max. to MIL-STD-883C method 3015.7 with ref. to VSS Maximum soldering conditions Symbol VDD VLCD VLOGIC VDISP TSTO Conditions -0.3V to 9V -0.3V to 10V -0.3V to VDD + 0.3V -0.3V to VLC +0.3V -65 to +150C
Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the voltage range. Unused inputs must always be tied to a defined logic voltage level. Operating Conditions
VSmax
1000V
TSmax
250C x 10s Table 1
Parameter Symbol Operating Temperature TA Logic supply voltage VDD LCD supply voltage VLCD
Min -40 2 2
Typ 5 5
Max Unit +85 C 6 V 8.5 V Table 2
Stresses above these listed maximum ratings may cause permanent damages to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. Electrical Characteristics VDD = 5V 10%, VLCD = 2 to 8.5V and TA = -40 to +85C, unless otherwise specified Parameter Symbol Test Conditions Min Dynamic supply current ILCD See note 1 Dynamic supply current IDD See note 1 at TA = 25C Dynamic supply current IDD See note 1 Dynamic supply current IDD See note 2 Control Signals DI, CLK, FR Input leakage IIN 0 < VIN < VDD Input capacitance CIN at TA = 25C Low level input voltage VIL 0 High level input voltage VIH 2.0 Data Output DO High level output voltage VOH IH = 2mA 2.4 Low level output voltage VOL IL = 2mA Driver Outputs S1 ... S60 Driver impedance (note 4) ROUT IOUT = 10A, VLCD = 7V Driver impedance (note 4) ROUT IOUT = 10A, VLCD = 3V Driver impedance (note 4) ROUT IOUT = 10A, VLCD = 2V Bias impedance V1, V2, V3 (note 5) RBIAS IOUT = 10A, VLCD = 7V Bias impedance V1, V2, V3 (note 5) RBIAS IOUT = 10A, VLCD = 3V Bias impedance V1, V2, V3 (note 5) RBIAS IOUT = 10A, VLCD = 2V DC output component VDC see Table 4a and 4b, VLCD =5V Note 1: Note 2: Note 3: Note 4: Note 5:
Typ 175 29 29 285 1 8
Max 250 35 50 350 100 0.8 VDD 0.4
Unit A A A A nA pF V V V V k k k k k k mV
Table 3
1 2.6 7 18 20 24 15
1.5 3.5 24 27 50
All outputs open, DI and CLK at VSS, FR = 400Hz, all other inputs at VDD All outputs open, DI at VSS, FR = 400Hz, fCLK = 1MHz All outputs open, all inputs at VDD This is the impedance between of the voltage bias level pins (V1, V2, or V3) and the output pins S1 to S60 when a given voltage bias level is driving the outputs (S1 to S60) This is the impedance seen at the segment pin. Outputs measured one at a time
Copyright (c) 2004, EM Microelectronic-Marin SA
2
www.emmicroelectronic.com
R
V6123
Column Drivers Outputs S1 to S60 S1 to S60 S1 to S60 S1 to S60 FR Polarity logic 1 logic 0 logic 1 logic 0 Column Data logic 1 logic 1 logic 0 logic 0 Measured | Sx* - VSS | | VLCD - Sx* | | VLCD - Sx* | | Sx* - VSS | Guaranteed | VLCD - Sx* | = | Sx* - VSS | 25mV | VLCD - Sx* | = | Sx* - VSS | 25mV
Table 4a
*Sx = the output number (ie. S1 to S60) Row Drivers Outputs S1 to Sn* S1 to Sn* S1 to Sn* S1 to Sn*
FR Polarity logic 1 logic 0 logic 1 logic 0
Row Data logic 1 logic 1 logic 0 logic 0
Measured | VLCD - Sx | | Sx - VSS | | Sx - VSS | | VLCD - Sx |
Guaranteed | VLCD - Sx | = | Sx - VSS | 25mV | VLCD - Sx | = | Sx - VSS | 25mV
Table 4b
*n = the V6123 mux programme number (ie. 2, 4 or 8) Timing Characteristics VDD = 5V 10%, VLCD = 2 to 8.5V and TA = -40C to +85C Parameter Symbol Test Conditions Clock high pulse width tCH Clock low pulse width tCL Clock and FR rise time tCR Clock and FR fall time tCF Data input setup time tDS Data input hold time tDH Data output propagation tPD CLOAD = 50pF STR pulse width tSTR FR (internal frame frequency) fFR (note 2) TA = 25C
Min 120 120 20 (note 1) 30 (note 1) 6 45
Typ
Max 2000 200 200 200 65
55
Unit ns ns ns ns ns ns ns s Hz
Table 5a
Note 1: tDS + tDH minimum must be 100ns. If tDS = 20ns then tDH 80ns Note 2: V6123 n, FR = n times the desired LCD refresh rate where n Is the V6123 mux mode number See Fig. 14, 15 for more details concerning frame frequency VDD = 2 to 6V, VLCD = 2 to 8.5V and TA = -40C to +85C Parameter Symbol Test Conditions Clock high pulse width tCH Clock low pulse width tCL Clock and FR rise time tCR Clock and FR fall time tCF Data input setup time tDS Data input hold time tDH Data output propagation tPD CLOAD = 50pF STR pulse width tSTR Note 1: tDS + tDH minimum must be 500ns. If tDS = 100ns then tDH 400ns
Min 0.5 0.5 100 (note 1) 150 (note 1) 16
Typ
Max 1.5 200 200 500
Unit s s ns ns ns ns ns s
Table 5b
Copyright (c) 2004, EM Microelectronic-Marin SA
3
www.emmicroelectronic.com
R
V6123
Timing Waveforms
Fig. 3
Clock Definition
Fig. 4
Programmation Data Bits and Data Transfer Cycle 0 1 Multiplex Ratio Command Bits 0 to 7 2 3 4 5
COL
6 Blank
7 SET
RAM Address
Bit2: COL bit configure the V6123 function as row and column driver or column driver only. Bit6: Blank bit forces all column outputs OFF. Bit7: SET bit forces all column outputs ON. Note: If bit 6 and 7 are both to 1L the chip is synchronized to row 1.
0 0 0 1 1
Mux Ratio (bit 0, 1) 1 Mux Mode 0 2 1 4 0 1 8
V6123 as a row and column driver, 68 bit load cycle, RAM address arising from command bits 3 to 5 Display RAM Address Command Bits 3 to 5 Mux Mux Mux prog. 2 prog. 4 prog. 8 000 000 000 001 001 001 010 010 011 011 100 101 110 111
LCD Row Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8
All mux mode programmation or COL states need 68 bit load cycles
Fig. 5
Copyright (c) 2004, EM Microelectronic-Marin SA
4
www.emmicroelectronic.com
R
V6123
Block Diagram
Int. Oscillator Gating FR External Frame 3 Mux Decoder + COL
Bit Sequencer1) 10000000 8 Bit Shift Reg. DO 60 Bit Shift Register Gating DI 8 Write Enable Lines CLK DI
8 Read Enable Lines
8 x 60 Bit Display RAM
Add. Decoder
Command Bits
60 Bit Display Latch
SET Blank
Gating FR VLCD V1 V2 V3 STR VSS
COL
LCD Wafeform Generator
60 Display Driver Outputs
S1 ... S60 2
Mux Decoder
Fig. 6
Copyright (c) 2004, EM Microelectronic-Marin SA
5
www.emmicroelectronic.com
R
V6123
Pin Assignment Name Function S1 ...S60 LCD outputs, see Table 7 V3 LCD voltage bias level 3 (note 1, 2) V2 LCD voltage bias level 2 (note 1) V1 LCD voltage bias level 1 (note 1) VLCD Power supply for the LCD FR AC I/O signal for LCD driver output DI Serial data input DO Serial data output CLK Data clock input VDD Power supply for logic VSS Supply GND
Table 6
Name S1 S2 S3 S4 S5 S6 S7 S8 S9..S60 V6123 (2) Row1 Row2 Col1 Col2 Col3 Col4 Col5 Col6 Col7..58
COL inactive COL active V6123 (4) V6123 (8) Row1 Row1 Col1 Row2 Row2 Col2 Row3 Row3 Col3 Row4 Row4 Col4 Col1 Row5 Col5 Col2 Row6 Col6 Col3 Row7 Col7 Col4 Row8 Col8 Col5..56 Col1..52 Col9..60
Table 7
Note 1: The V6123 has internal voltage bias level generation. When driving large pixels, an external resistor divider chain can be connected to the voltage bias level inputs to obtain enhanced display contrast. See Fig 11, 12 and 13. The external resistor divider ratio should be in accordance with the internal resistor ratio (see Table 8). Note 2: V3 is connected internally to VSS on the V6123 mux mode 4.
LCD Voltage Bias Levels
LCD Drive Type LCD Bias Configuration
VOP (note1) VOFF (rms)
VON (rms) VOFF (rms)
V6123 (2) n=2 1:2 MUX
5 Levels
2n = 3.69 1 1- n
n +1 = 2.41 n -1
VLCD
R
V1
R
V2
R
V6123 (4) n=4 1:4 MUX
Bias 4 Levels
3
1+
8 = 1.73 n
VSS
V6123 (8) n=8 1:8 MUX
1/4 Bias 5 Levels
4 1+ 3 n
= 3.4
n + 15 = 1.446 n+3
Table 8
Note 1: VOP = VLCD - VSS
Copyright (c) 2004, EM Microelectronic-Marin SA
6
www.emmicroelectronic.com
R
V6123
Row and Column Multiplexing Waveform V6123 (2)
VOP = VLCD - VSS, VSTATE = VCOL - VROW
Fig. 7
Copyright (c) 2004, EM Microelectronic-Marin SA
7
www.emmicroelectronic.com
R
V6123
Row and Column Multiplexing Waveform V6123 (4)
VOP = VLCD - VSS, VSTATE = VCOL - VROW
Fig. 8
Copyright (c) 2004, EM Microelectronic-Marin SA
8
www.emmicroelectronic.com
R
V6123
Row and Column Multiplexing Waveform V6123 (8)
VOP = VLCD - VSS, VSTATE = VCOL - VROW
Fig. 9
Copyright (c) 2004, EM Microelectronic-Marin SA
9
www.emmicroelectronic.com
R
V6123
Functional Description
Supply Voltages VLCD, VDD, VSS The voltage between VDD and VSS is the supply voltage for the logic and the interface. The voltage between VLCD and VSS is the supply voltage for the LCD and is used for the generation of the internal LCD bias level have a maximum impedance of 30K for a voltage from 3 to 8.5V. Without external connections to the V1, V2, V3 bias level inputs, the V6123 can drive most medium sized LCD (pixel area 2 up to 4'000mm ). For displays with a wide variation in pixel sizes the configuration shown in Fig. 12 can give enhanced contrast by giving faster pixel switching times. On changing the row polarity (see Fig. 7, 8 and 9) the parallel capacitors lower the impedance of the bias level generation to the peak current, giving faster pixel charge times and thus a higher RMS "on" value. A higher RMS "on" value can give better contrast. If for a given LCD size and operating voltage, the "off" pixels appear "on", or there is poor contrast, then an external bias level generation circuit can be used with the V6123. An external bias generation circuit can lower the bias level impedance and hence improve the LCD contrast (see Fig.11). The optimum values of R, Rx and C, vary according to the LCD size used and VLCD. They are best determined through actual experimentation with the LCD. For LCD with very large average pixel area (eg. up to 2 10'000mm ) the bias level configuration shown in Fig. 13 should be used. When V6123 are cascaded connect the V1, V2 and V3 bias inputs as shown in Fig. 10. The pixel load is averaged across all the cascaded drivers. This will give enhanced display contrast as the effective bias level source impedance is the parallel combination of the total number of drivers. For example, if two V6123 are cascaded as shown in Fig. 10, then the maximum bias level impedance becomes 15 k for a VLCD voltage from 3 to 8.5V. Table 8 shows the relationship between V1, V2 and V3 for the multiplex rates 2, 4 and 8. Note that VLCD > V1 > V2 > V3 for the V6123 2 and 8 mux programmed, and for the V6123 4 mux programmed, VLCD > V1 > V2, and V3 = VSS. Data Input/Output The data input pin, DI, is used to load serial data into the V6123. The serial data word length is 68 bits. Data is loaded in inverse numerical order, the data for bit 68 is loaded first with the data for bit 1 last. The column data bits are loaded first and then the command byte, (see Fig 5). The data output pin, DO, is used in cascaded application (see Fig. 10). DO transfers the data to the next cascaded chip. The data at DO is equal to the data at DI delayed by 68 clock periods. In order to cascade V6123s, the DO of one chip must be connected to DI of the following chip (see Fig. 10). In cascaded applications the data for the last V6123 (the one that does not have DO connected) must be loaded first and the data for the first V6123 (its DI connected to the processor) loaded last. The display RAM word length is 60 bits (see Fig. 6). Each LCD row has a corresponding display RAM address which provides the column data (on or off) when the row is selected (on). When down loading data to the V6123 any display RAM address can be chosen. Display RAM address is given by command bits 3 to 5. Bit 6 forces all column outputs at 0L (display OFF). Bit 7 forces all
Copyright (c) 2004, EM Microelectronic-Marin SA
column outputs at 1L (display ON). If bit 7 (SET) and bit 6 (BLANK) are both active, the initialization function is activated. This function is used to xynchronize the chip at row one. The command bit 2 (COL) define the V6123 as a row and column driver or column driver only. The V6123 functions as row and column driver while the bit 2 (COL) is inactive. When active the bit 2 configures the V6123 to function as column driver only. The former row output function as column outputs. In cascaded applications one V6123 should be used in the row and column configuration ( COL inactive) and the rest as pure column drivers ( COL active) (see Fig. 10). Note when cascading V6123s never cascade one mux mode no. with another. If a V6123 8 mux programmed is used to drive the rows then only V6123 8 mux programmed can be cascaded with it. The command bits, bit 1 and bit 0, define the mux mode (see Fig. 5).
CLK input The clock input is used to clock the DI serial data into the shift register, to latch the data from the shift register into the RAM. After loading data into the shift register, the clock has to stay 0 logic during TSTR. After TSTR pulse, the data are latched into the RAM. FR Input / Output The frame frequency is realized by an internal RC oscillator with a typical value of 55 Hz. The internal row frequency changes with the number of rows (FROW = 55 x n, where n = 2, 4 or 8). When bit 2 ( COL ) is inactive (row and column driver), the frame frequency is given by the internal oscillator. This frequency can also be used at FR output to drive cascaded V6123. When bit 2 ( COL ) is active (column driver only), the frame frequency is external then the frequency is given by the row and column driver directly to the FR input. In cascaded applications, the row and column driver (FR, output) give the frame frequency to all the cascaded chip (FR, input). Driver Outputs S1 to S60 There are 60 LCD driver outputs on the V6123. When bit 2 ( COL ) is inactive the outputs S1 to Sn function as row drivers and the outputs S(n+1) to S60 function as column drivers. Where n is the V6123 mux mode no. (2,4 or 8). When bit 2 ( COL ) is active all 60 outputs function as column drivers (see table 6). There is a one to one relationship between the display RAM and the LCD driver outputs. Each pixel (segment) driven by the V6123 on the LCD has a display RAM bit which corresponds to it. Setting the bit turns the segment "on" and clearing it turns it "off ". Power-Up On power up the data in the shift registers, the display RAM, the sequencer driving the 2/4/8 rows and the 60 bit display latches are undefined.
10
www.emmicroelectronic.com
R
V6123
Applications
Two V6123 8 Mux Programmed Cascaded
By connecting the V1, V2 and V3 bias inputs as shown, the pixel load is averaged across all the drivers. The effective bias level source impedance is the parallel combination of the total number of drivers. For example, if two V6123 are cascaded as above, then the maximum bias level impedance becomes 15 k. Fig. 10
V6123 8 Mux Programmed with External Resistor Divider Bias Generation
Example set values: R = 3.3 - 10 k C = 2.2 - 47 nF Rx is given by the formula: Rx = 4R ((VDISP/VLCD)-1) = 10 - 30 k Fig. 11
Copyright (c) 2004, EM Microelectronic-Marin SA
11
www.emmicroelectronic.com
R
V6123
Enhanced Switching from the V6123
Temperature compensation/ Constrast adjustment
Bias Configuration for Large LCD
C = 1F Rx is given by the formula: Rx = 4(24 k) ((VDISP/VLCD) - 1)
Large LCD example: VOP = 5V, average pixel active area = up to 10'000 mm2, display refresh rate = 55 Hz For a single V6123 4 mux programmed driving such an LCD, the voltage follower buffer (opamp) requirement is: peak current 1.8 mA steady state current typically 150 A Fig. 12 Fig. 13
Frame Frequency vs. Temperature at VDD = 4.5V
Fig. 14
Frame Frequency vs. VDD at TA = 25C
Fig. 15
Copyright (c) 2004, EM Microelectronic-Marin SA
12
www.emmicroelectronic.com
R
V6123
Application Example
This table (Table 9) shows how to use the V6123 with a given initialization for Chip-on-Glass. Rows "Data" show the logical value to affect pad DI for each falling edge of pad CLK. After loading data into the shift register, the clock has to stay logic 0 during tSTR. After the tSTR pulse the data are latched into the RAM.
Display Data
Bit No Data 67 0 66 1 65 1 64 1 63 0 62 0 61 0 60 1 59 0 58 1 57 1 56 1 55 0 54 1 53 1 52 1 51 0 .. .. 20 0 19 0 18 1 17 0 16 1 15 X
8 Bits "don't care"
14 X 13 X 12 X 11 X 10 X 9 X 8 X
S1 S2 S3 S4 S5 S6 S7 S8
= undefined = pixel "OFF" = pixel "ON"
Result
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.01 Display Data
Bit No Data 67 0 66 1 65 0 64 0 63 0 62 0 61 1 60 1 59 0 58 0 57 0 56 1 55 0 54 0 53 0 52 1 51 0 .. .. 20 0 19 0 18 1 17 0 16 1 15 X
8 Bits "don't care"
14 X 13 X 12 X 11 X 10 X 9 X 8 X
S1 S2 S3 S4 S5 S6 S7 S8
= undefined = pixel "OFF" = pixel "ON"
Result
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.02 Display Data
Bit No Data 67 0 66 1 65 0 64 0 63 0 62 1 61 1 60 1 59 0 58 0 57 0 56 1 55 0 54 0 53 0 52 1 51 0 .. .. 20 0 19 0 18 1 17 0 16 1 15 X
8 Bits "don't care"
14 X 13 X 12 X 11 X 10 X 9 X 8 X
S1 S2 S3 S4 S5 S6 S7 S8
= undefined = pixel "OFF" = pixel "ON"
Result
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.03
Copyright (c) 2004, EM Microelectronic-Marin SA
13
www.emmicroelectronic.com
Write Row 3 Mux 8
Command Byte 7654321 0001011 Bit 7, 6 = 0, 0 : Bit 3 to 5 = 0, 1, 0 : Bit 2 = 1 : Bit 0,1 = 1,1 :
0 1 no set, no blank data sent to row 3 of the RAM row and column driver configuration mux 8
Description
Write Row 2 Mux 8
Command Byte 7654321 0010011 Bit 7, 6 = 0, 0 : Bit 3 to 5 = 0, 0, 1 : Bit 2 = 1 : Bit 0,1 = 1,1 :
0 1 no set, no blank data sent to row 2 of the RAM row and column driver configuration mux 8
Description
Write Row 1 Mux 8
Command Byte 7654321 0000011 Bit 7, 6 = 0, 0 : Bit 3 to 5 = 0, 0, 0 : Bit 2 = 1 : Bit 0,1 = 1,1 :
0 1
Last send no set, no blank data sent to row 1 of the RAM row and column driver configuration mux 8
Description
R
V6123
Display Data
Bit No Data 67 0 66 1 65 1 64 1 63 0 62 0 61 0 60 1 59 0 58 1 57 1 56 1 55 0 54 0 53 1 52 1 51 0 .. .. 20 0 19 0 18 1 17 0 16 1 15 X
8 Bits "don't care"
14 X 13 X 12 X 11 X 10 X 9 X 8 X
S1 S2 S3 S4 S5 S6 S7 S8
= undefined = pixel "OFF" = pixel "ON"
Result
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.04 Display Data
Bit No Data 67 0 66 1 65 0 64 1 63 0 62 0 61 0 60 1 59 0 58 1 57 0 56 0 55 0 54 0 53 0 52 1 51 0 .. .. 20 0 19 0 18 1 17 0 16 1 15 X
8 Bits "don't care"
14 X 13 X 12 X 11 X 10 X 9 X 8 X
S1 S2 S3 S4 S5 S6 S7 S8
= undefined = pixel "OFF" = pixel "ON"
Result
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.05 Display Data
Bit No Data 67 0 66 1 65 0 64 1 63 0 62 0 61 0 60 1 59 0 58 1 57 0 56 0 55 0 54 0 53 0 52 1 51 0 .. .. 20 0 19 0 18 1 17 0 16 1 15 X
8 Bits "don't care"
14 X 13 X 12 X 11 X 10 X 9 X 8 X
S1 S2 S3 S4 S5 S6 S7 S8
= undefined = pixel "OFF" = pixel "ON"
Result
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.06
Copyright (c) 2004, EM Microelectronic-Marin SA
14
www.emmicroelectronic.com
Write Row 6 Mux 8
Command Byte 7654321 0010111 Bit 7, 6 = 0, 0 : Bit 3 to 5 = 1, 0, 1 : Bit 2 = 1 : Bit 0,1 = 1,1 :
0 1 no set, no blank data sent to row 6 of the RAM row and column driver configuration mux 8
Description
Write Row 5 Mux 8
Command Byte 7654321 0000111 Bit 7, 6 = 0, 0 : Bit 3 to 5 = 1, 0, 0 : Bit 2 = 1 : Bit 0,1 = 1,1 :
0 1 no set, no blank data sent to row 5 of the RAM row and column driver configuration mux 8
Description
Write Row 4 Mux 8
Command Byte 7654321 0011011 Bit 7, 6 = 0, 0 : Bit 3 to 5 = 0, 1, 1 : Bit 2 = 1 : Bit 0,1 = 1,1 :
0 1 no set, no blank data sent to row 4 of the RAM row and column driver configuration mux 8
Description
R
V6123
Display Data
Bit No Data 67 0 66 1 65 1 64 1 63 0 62 0 61 0 60 1 59 0 58 1 57 1 56 1 55 0 54 1 53 1 52 1 51 0 .. .. 20 0 19 0 18 0 17 1 16 0 15 X
8 Bits "don't care"
14 X 13 X 12 X 11 X 10 X 9 X 8 X
S1 S2 S3 S4 S5 S6 S7 S8
= undefined = pixel "OFF" = pixel "ON"
Result
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.07 Display Data
Bit No Data 67 0 66 0 65 0 64 0 63 0 62 0 61 0 60 0 59 0 58 0 57 0 56 0 55 0 54 0 53 0 52 0 51 0 .. .. 20 0 19 0 18 0 17 0 16 0 15 X
8 Bits "don't care"
14 X 13 X 12 X 11 X 10 X 9 X 8 X
S1 S2 S3 S4 S5 S6 S7 S8
= undefined = pixel "OFF" = pixel "ON"
Result
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.08
Bit No Data Description
S1 S2 S3 S4 S5 S6 S7 S8
= undefined = pixel "OFF" = pixel "ON"
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.09
Copyright (c) 2004, EM Microelectronic-Marin SA
15
www.emmicroelectronic.com
Command Byte only: Set
Command Byte 7654321 0011111 Bit 7, 6 = 1, 0 : Bit 3 to 5 = 1, 1, 1 : Bit 2 = 1 : Bit 0,1 = 1,1 :
0 1 SET, no blank data sent to row 8 of the RAM row and column driver configuration mux 8
Result
Write Row 8 Mux 8
Command Byte 7654321 0011111 Bit 7, 6 = 0, 0 : Bit 3 to 5 = 1, 1, 1 : Bit 2 = 1 : Bit 0,1 = 1,1 :
0 1 no set, no blank data sent to row 8 of the RAM row and column driver configuration mux 8
Description
Write Row 7 Mux 8
Command Byte 7654321 0001111 Bit 7, 6 = 0, 0 : Bit 3 to 5 = 1, 1, 0 : Bit 2 = 1 : Bit 0,1 = 1,1 :
0 1 no set, no blank data sent to row 7 of the RAM row and column driver configuration mux 8
Description
R
V6123
Table 9 cont. Display Data Bit No Data Description Command Byte 7654321 0111111 Bit 7, 6 = 0, 1 : Bit 3 to 5 = 1, 1, 1 : Bit 2 = 1 : Bit 0,1 = 1,1 :
S1 S2 S3 S4 S5 S6 S7 S8
8 Bits "don't care"
no set, BLANK data sent to row 8 of the RAM row and column driver configuration mux 8
= undefined = pixel "OFF" = pixel "ON"
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.10
Display Data Bit No Data Description Command Byte 7654321 1100011 Bit 7, 6 = 1, 1 : Bit 3 to 5 = 0, 0, 0 : Bit 2 = 1 : Bit 0,1 = 1,1 :
S1 S2 S3 S4 S5 S6 S7 S8
8 Bits "don't care"
no set, no blank Synchronize the chip at row 1 data sent to row 8 of the RAM, you have to rewrite row 8 of the RAM row and column driver configuration mux 8
= undefined = pixel "OFF" = pixel "ON"
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.11
Display Data
Bit No Data 67 0 66 0 65 0 64 0 63 0 62 0 61 0 60 0 59 0 58 0 57 0 56 0 55 0 54 0 53 0 52 0 51 0 .. .. 20 0 19 0 18 0 17 0 16 0 15 X
8 Bits "don't care"
14 X 13 X 12 X 11 X 10 X 9 X 8 X
no set, no blank Synchronize the chip at row 1 data sent to row 3 of the RAM row and column driver configuration mux 8
= undefined = pixel "OFF" = pixel "ON"
S1 S2 S3 S4 S5 S6 S7 S8
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.12
Copyright (c) 2004, EM Microelectronic-Marin SA
16
www.emmicroelectronic.com
Synchro Rewrite Row 8 Mux 8
Bit No Data Description
Command Byte 7654321 1111111 Bit 7, 6 = 1, 1 : Bit 3 to 5 = 1, 1, 1 : Bit 2 = 1 : Bit 0,1 = 1,1 :
0 1
Result
Command Byte only: Synchro
0 1
Result
Command Byte only: Blank
0 1
Result
R
V6123
Table 9 cont. Display Data
Bit No Data 67 0 66 1 65 0 64 1 63 0 62 1 61 0 60 1 59 0 58 1 57 0 56 1 55 0 54 1 53 0 52 1 51 0 .. .. 20 1 19 0 18 1 17 0 16 1 15 0
8 Bits "don't care"
14 1 13 0 12 1 11 X 10 X 9 X 8 X
no set, no blank data sent to row 1 of the RAM row and column driver configuration mux 4
= undefined = pixel "OFF" = pixel "ON"
Result
S1 S2 S3 S4
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.13
Display Data
Bit No Data 67 1 66 0 65 1 64 0 63 1 62 0 61 1 60 0 59 1 58 0 57 1 56 0 55 1 54 0 53 1 52 0 51 1 .. .. 20 0 19 1 18 0 17 1 16 0 15 1
8 Bits "don't care"
14 0 13 1 12 0 11 X 10 X 9 X 8 X
no set, no blank data sent to row 2 of the RAM row and column driver configuration mux 4
= undefined = pixel "OFF" = pixel "ON"
Result
S1 S2 S3 S4
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.14
Display Data
Bit No Data 67 1 66 0 65 1 64 0 63 1 62 0 61 1 60 0 59 1 58 0 57 1 56 0 55 1 54 0 53 1 52 0 51 1 .. .. 20 0 19 1 18 0 17 1 16 0 15 1
8 Bits "don't care"
14 0 13 1 12 0 11 X 10 X 9 X 8 X
no set, no blank data sent to row 3 of the RAM row and column driver configuration mux 4
= undefined = pixel "OFF" = pixel "ON"
Result
S1 S2 S3 S4
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.15
Copyright (c) 2004, EM Microelectronic-Marin SA
17
www.emmicroelectronic.com
Write Row 3 Mux 4
Command Byte 7654321 0001011 Bit 7, 6 = 0, 0 : Bit 3 to 5 = 0, 1, 0 : Bit 2 = 1 : Bit 0,1 = 0,1 :
0 0
Description
Write Row 2 Mux 4
Command Byte 7654321 0001011 Bit 7, 6 = 0, 0 : Bit 3 to 5 = 0, 0, 1 : Bit 2 = 1 : Bit 0,1 = 0,1 :
0 0
Description
Write Row 1 Mux 4
Command Byte 7654321 0000011 Bit 7, 6 = 0, 0 : Bit 3 to 5 = 0, 0, 0 : Bit 2 = 1 : Bit 0,1 = 0,1 :
0 0
Description
R
V6123
Table 9 cont. Display Data
Bit No Data 67 1 66 0 65 1 64 0 63 1 62 0 61 1 60 0 59 1 58 0 57 1 56 0 55 1 54 0 53 1 52 0 51 1 .. .. 20 0 19 1 18 0 17 1 16 0 15 1
8 Bits "don't care"
14 0 13 1 12 0 11 X 10 X 9 X 8 X
no set, no blank data sent to row 4 of the RAM row and column driver configuration mux 4
= undefined = pixel "OFF" = pixel "ON"
Result
S1 S2 S3 S4
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.16
Display Data
Bit No Data 67 0 66 1 65 0 64 1 63 0 62 1 61 0 60 1 59 0 58 1 57 0 56 1 55 0 54 1 53 0 52 1 51 0 .. .. 20 1 19 0 18 1 17 0 16 1 15 0
8 Bits "don't care"
14 1 13 0 12 1 11 0 10 1 9 X 8 X
no set, no blank data sent to row 1 of the RAM row and column driver configuration mux 2
= undefined = pixel "OFF" = pixel "ON"
Result
S1 S2
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.17
Display Data
Bit No Data 67 0 66 1 65 0 64 1 63 0 62 1 61 0 60 1 59 0 58 1 57 0 56 1 55 0 54 1 53 0 52 1 51 0 .. .. 20 1 19 0 18 1 17 0 16 1 15 0
8 Bits "don't care"
14 1 13 0 12 1 11 0 10 1 9 X 8 X
no set, no blank data sent to row 2 of the RAM row and column driver configuration mux 2
= undefined = pixel "OFF" = pixel "ON"
Result
S1 S2
S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
S12 S11 S10 S09
Fig. 16.18
Copyright (c) 2004, EM Microelectronic-Marin SA
18
www.emmicroelectronic.com
Write Row 2 Mux 2
Command Byte 7654321 0010010 Bit 7, 6 = 0, 0 : Bit 3 to 5 = 0, 0, 0 : Bit 2 = 1 : Bit 0,1 = 0,0 :
0 0
Description
Write Row 1 Mux 2
Command Byte 7654321 0000010 Bit 7, 6 = 0, 0 : Bit 3 to 5 = 0, 0, 0 : Bit 2 = 1 : Bit 0,1 = 0,0 :
0 0
Description
Write Row 4 Mux 4
Command Byte 7654321 0011011 Bit 7, 6 = 0, 0 : Bit 3 to 5 = 0, 1, 1 : Bit 2 = 1 : Bit 0,1 = 0,1 :
0 0
Description
R
V6123
Package Information
Dimensions of Chip Form
All dimensions in m Thickness: Bump size: Chip size: Note: 11 mils typ. Output pad = 110 x 110 micron, Input pad = 120 x 120 micron [X x Y] 8864 x 1981 micron or 349 x 78 mils The origin (0,0) is the lower left coordinate of center pads The lower left corner of the chip shows distances to origin
Fig. 17
Ordering Information The V6123 is available in the following packages:
Chip form Bumped form : : V6123 Chip V6123 Bumped
When ordering please specify the complete part number and package.
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version. (c) EM Microelectronic-Marin SA, 09/04, Rev. E Copyright (c) 2004, EM Microelectronic-Marin SA 19 www.emmicroelectronic.com

▲Up To Search▲

Price & Availability of V6123

	To Download V6123 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .